From 0ba991750314310a5e53b0d8135aef5b1352b261 Mon Sep 17 00:00:00 2001 From: Marvin Borner Date: Wed, 20 Nov 2019 22:17:48 +0100 Subject: Began two-stage hdd bootloader and os installer --- src/kernel/interrupts/interrupts.h | 12 ++++++++++++ src/kernel/interrupts/isr.c | 9 ++++++++- 2 files changed, 20 insertions(+), 1 deletion(-) (limited to 'src/kernel/interrupts') diff --git a/src/kernel/interrupts/interrupts.h b/src/kernel/interrupts/interrupts.h index 80c9b27..cd96b7c 100644 --- a/src/kernel/interrupts/interrupts.h +++ b/src/kernel/interrupts/interrupts.h @@ -1,6 +1,8 @@ #ifndef MELVIX_INTERRUPTS_H #define MELVIX_INTERRUPTS_H +#include + /** * Initialize the Interrupt Descriptor Table with 256 entries */ @@ -20,6 +22,16 @@ void idt_set_gate(unsigned char num, unsigned long base, unsigned short sel, uns */ void isrs_install(); +/** + * Ignore interrupt + */ +void isr_ignore(uint8_t int_no); + +/** + * Un-ignore interrupt + */ +void isr_remember(uint8_t int_no); + /** * Registers that get passed into an IRQ handler */ diff --git a/src/kernel/interrupts/isr.c b/src/kernel/interrupts/isr.c index d03a6de..0893df7 100644 --- a/src/kernel/interrupts/isr.c +++ b/src/kernel/interrupts/isr.c @@ -69,6 +69,8 @@ extern void isr30(); extern void isr31(); +uint32_t ignored_isr[8] = {0}; + // Install ISRs in IDT void isrs_install() { idt_set_gate(0, (unsigned) isr0, 0x08, 0x8E); @@ -151,7 +153,7 @@ const char *exception_messages[] = { // Master exception/interrupt/fault handler - halt via panic void fault_handler(struct regs *r) { - if (r->int_no < 32) { + if (r->int_no < 32 && !(ignored_isr[r->int_no / 32] & (1 << (r->int_no % 32)))) { uint32_t faulting_address; asm volatile("mov %%cr2, %0" : "=r" (faulting_address)); @@ -176,3 +178,8 @@ void fault_handler(struct regs *r) { panic(message); } } + + +void isr_ignore(uint8_t int_no) { ignored_isr[int_no / 32] |= 1 << (int_no % 32); } + +void isr_remember(uint8_t int_no) { ignored_isr[int_no / 32] &= ~(1 << (int_no % 32)); } -- cgit v1.2.3